1. Field of the Invention
The present invention relates, in general, to Magnetic Random Access Memory (MRAM), and, more particularly, to a non-volatile memory device which uses magnetoresistance variation.
2. Description of the Related Art
Dynamic Random Access Memory (DRAM), which is a representative memory device that is currently widely used, is advantageous in that high-speed operation and high integration are possible, but is disadvantageous in that, since DRAM is volatile memory, data is lost when power is turned off, and in that, since data must be continuously rewritten through a data refresh operation even during the operation of the DRAM, power loss increases. On the other hand, flash memory having characteristics of non-volatility and high integration is disadvantageous in that the operating speed is low. In contrast, magnetoresistive memory (MRAM) which stores information using the difference between magnetoresistances is advantageous in that high integration is possible while characteristics of non-volatility and high-speed operation are realized.
Meanwhile, MRAM refers to a non-volatile memory device using magnetoresistance variation corresponding to the magnetization direction between ferromagnetic bodies. Currently, cell structures that are most frequently employed as the cells of MRAM may include a Giant Magneto-Resistance (GMR) device using GMR effect, and a Magnetic Tunnel Junction (MTJ) device using Tunnel Magneto-Resistance (TMR) effect. In addition, there is a spin-valve device which reinforces a ferromagnetic layer with a permanent magnet and employs a soft magnetic layer as a free layer to overcome the disadvantage of a GMR device. In particular, since an MTJ device has a high operation-speed and low power consumption and is used in place of the capacitor of DRAM, the MTJ device can be applied to graphic and mobile devices having low-power consumption and high speed.
Generally, a magnetoresistive device has low resistance when the spin directions of two magnetic layers (that is, the directions of magnetic momentums) are identical to each other, whereas it has high resistance when the spin directions are opposite each other. In this way, bit data can be written in a magnetoresistive memory device using the resistance change of a cell changes depending on the magnetization states of magnetic layers. Magnetoresistive memory having an MTJ structure will be described by way of an example. In an MTJ memory cell having a structure composed of a ferromagnetic layer/insulating layer/ferromagnetic layer, when electrons, passed through the first ferromagnetic layer, pass through the insulating layer used as a tunneling barrier, the tunneling probability changes depending on the magnetization direction of the second ferromagnetic layer. That is, when the magnetization directions of two ferromagnetic layers are parallel, tunneling current is maximized, whereas, when they are anti-parallel, tunneling current is minimized. For example, it can be considered that, when resistance is high, data ‘1’ is written, and when resistance is low, data ‘0’ is written.
FIGS. 1A and 1B are a circuit diagram and a sectional view, respectively, of an MTJ unit cell constituting a magnetoresistive memory. As shown in FIGS. 1A and 1B, an MTJ device 10 includes a pinned magnetic layer 11 having a pinned magnetization direction, a free magnetic layer 13 having a magnetization direction which can be changed to be parallel or anti-parallel with that of the pinned magnetic layer 11, and a non-magnetic layer, that is, a magnetic tunnel barrier layer 12 interposed between the pinned magnetic layer 11 and the free magnetic layer 13. Further, one Metal Oxide Semiconductor (MOS) transistor Tr, used as a switching device, is connected in series with one end of the MTJ device 10. The MOS transistor Tr is composed of a gate electrode 20 formed by disposing a gate insulating layer 22 on the top of a semiconductor substrate 100 having a first conduction type, and first and second diffusion regions 40 each having a second conduction type. Here, reference numeral 24 denotes spacers formed on the sidewalls of the gate electrode 20, and reference numeral 50 denotes a contact plug for electrically connecting the MTJ device 10 to the diffusion regions 40. FIG. 1B illustrates an N-channel MOS transistor by way of example.
In the structure of the conventional MTJ memory cell shown in FIGS. 1A and 1B, current is applied to a transistor Tr through a source line SL, and the applied current is controlled within the transistor Tr in response to a signal input through a word line WL. Further, the current controlled within the transistor Tr is output to the MTJ device 10, so that the magnetization direction of the free magnetic layer 13 is changed, and data “1” or “0” is written according to the parallel or anti-parallel state of the magnetization directions of the free magnetic layer 13 and the pinned magnetic layer 11. The data written in this way is read through a bit line BL.
In such a current switching-type magnetoresistive memory device, a single memory cell for storing information generally includes a single MTJ device and a select transistor for enabling the writing or reading of data by selecting the MTJ device. Therefore, in order to write information to be stored in the MTJ device, very high current must be caused to bidirectionally flow through the MTJ device. However, it is difficult to drive current sufficiently high to write information in the MTJ device by using a micro-transistor required for the implementation of high-integration memory.
FIG. 2 illustrates the current-voltage characteristics of a MOS transistor formed in the conventional magnetoresistive memory device shown in FIGS. 1A and 1B. With reference to FIG. 2, current-voltage characteristics at a certain gate voltage are described. As a source-drain voltage VD increases, current ID is saturated. That is, at region P, channel impedance increases as the channel of the MOS transistor is pinched off, so that the MOS transistor is operated in a region of saturated current flow. When a MOS transistor is manufactured to be of micro size for the purpose of the implementation of a high-integration memory device, the channel of the MOS transistor is shortened, and such a saturation phenomenon occurs even at a low voltage. In the region P of saturated current flow, it is difficult to obtain high current due to the saturation of current even if a drain-source voltage is increased.
Therefore, when a MOS transistor is formed on a bulk silicon substrate as in the case of the prior art, the size of the MOS transistor must be increased in order to obtain a current sufficiently high to write information in an MTJ device, thus obstructing the high-integration of a memory device. Further, when reading data, the difference between MOS currents is recognized by the difference between the drain voltages which occurs due to the difference between the resistances of the MTJ device. As shown in FIG. 2, since resistance difference ΔR is not large, read voltage difference Vr is small, and thus the current difference between data “1” and “0” generated at this time falls within a range of only several tens of percent.
Therefore, in order to increase the integration of the magnetoresistive memory device, there is a need to reduce an area in which a memory cell is formed. However, when the size of the cell is reduced, the current driving capability of a MOS transistor which is a switching device may be deteriorated, so that it may be difficult to ensure a sufficient amount of current required for the driving of the MTJ device. As a result, in a conventional magnetoresistive memory device, a device, having a very wide area in which a MOS transistor is formed, is used, and a sensing circuit for detecting a small current difference is greatly complicated and occupies a large space.
In implementing a high-integration magnetoresistive memory device, a select transistor is manufactured in an area corresponding to the size of an MTJ device, and current sufficiently high to write data in the MTJ device is desired. However, in a conventional magnetoresistive memory device, an area in which a MOS transistor is formed decreases due to the reduction of a cell area attributable to high integration, so that the current driving capability of the transistor is deteriorated, thus making it difficult to achieve the high integration of a magnetoresistive memory device.